View K4S281632K_4509208.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

synchronous dram rev. 1.23 march 2009 1 of 15 k4s280832k K4S281632K 128mb k-die sdram specification 54 tsop-ii (rohs compliant) with lead-free & halogen-free * samsung electronics reserves the right to change products or specification without notice. information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or other- wise, to any intellectual property rights in samsung products or technol- ogy. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about sa msung products, contact your nearest samsung office. 2. samsung products are not intended for use in life support, critical care, me dical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmen tal procurement to which special terms or provisions may apply.
synchronous dram rev. 1.23 march 2009 2 of 15 k4s280832k K4S281632K 1.0 features ............ ................ ................. .............. .............. .............. .............. ............. ............. ......... 4 2.0 general description ....... ................ ................. ................ ................ ................. .............. .............. 4 3.0 ordering information ..... ................ ................. ................ ................ ................. ............... ............. 4 4.0 package physical dimension .......... ................ .............. .............. .............. .............. .............. ..... 5 5.0 functional block diagram ........... ................ .............. .............. ............... .............. .............. ......... 6 6.0 pin configuration (top view) ............. ................. ................ ................. ................ ............. ........ 7 7.0 pin function desc ription .............. .............. .............. .............. ............... .............. ............. .......... 7 8.0 absolute maximum ratings .......... ................. ................ .............. .............. .............. ............. ...... 8 9.0 dc operating conditions ... ................ ................ ................. ................ ................. .............. ......... 8 10.0 capacitance ............. ................. ................ ................ ................. ................ ............... ........... ....... 8 11.0 dc characteristics (x8) . ................. ................ ................ ................. ................ ............... ........... 9 12.0 dc characteristics (x16) ................ ................ ................ ................. ................ ................ ........ 10 13.0 ac operating test conditions ....... ................ .............. .............. .............. .............. .............. ... 11 14.0 operating ac parameter .. ................ ................ ................. ................ ................. ............... ...... 11 15.0 ac characteristics ....... ................ ................. ................ ................ ................. .............. ............ 12 16.0 dq buffer output drive characteristics ....... ................ ................. .............. .............. ............ 12 17.0 ibis specification ....... ................ ................ ................. ................ ................. .............. .............. 13 18.0 simplified truth ta ble ............... .............. .............. .............. .............. .............. .............. .......... 15 table of contents
synchronous dram rev. 1.23 march 2009 3 of 15 k4s280832k K4S281632K revision history revision month year history 1.0 february 2007 - release revision 1.0 spec 1.1 november 2007 - revised typo of package dimension - added the comment of halogen-free supporting 1.2 february 2008 - added -50 bin(200mhz) dram 1.21 march 2008 - added package pin out lead width 1.22 august 2008 - corrected typo and font format 1.23 march 2009 - deleted organization x4
synchronous dram rev. 1.23 march 2009 4 of 15 k4s280832k K4S281632K part no. orgainization max freq. interface package k4s280832k-u *1 c/l75 16mb x 8 133mhz (cl=3) lvttl 54pin tsop(ii) lead-free & halogen-free *1 K4S281632K-uc/l50 8mb x 16 200mhz(cl=3) K4S281632K-uc/l60 8mb x 16 166mhz (cl=3) K4S281632K-uc/l75 8mb x 16 133mhz (cl=3) the k4s280832k / K4S281632K is 134,217,728 bits synchronous high data rate dynamic ram organized as 4 x 4,194,304 words by 8 bits / 4 x 2,097,152 words by 16 bits, fabricated with samsung s high performance cmos technology. synchronous design allows precise cycle control with the use of system clock i/o transactions are possible on ev ery clock cycle. rang e of operating frequ encies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high p erfor- mance memory system applications. ? jedec standard 3.3v power supply ? lvttl compatible with multiplexed address ? four banks operation ? mrs cycle with address key programs -. cas latency (2 & 3) -. burst length (1, 2, 4, 8 & full page) -. burst type (sequential & interleave) ? all inputs are sampled at the positive going edge of the system clock. ? burst read single -bit write operation ? dqm (x8) & l(u)dqm (x16) for masking ? auto & self refresh ? 64ms refresh period (4k cycle) ? 54pin tsop ii lead-free and halogen-free package ? rohs compliant 4m x 8bit x 4 banks / 2m x 16bit x 4 banks sdram row & column address configuration organization row address column address 16mx8 a0~a11 a0-a9 8mx16 a0~a11 a0-a8 1.0 features 2.0 general description 3.0 ordering information note 1 : 128mb k-die sdr drams support lead-free & halogen-free package with lead-free package code(-u).
synchronous dram rev. 1.23 march 2009 5 of 15 k4s280832k K4S281632K 4.0 package physical dimension 54pin tsop(ii) package dimension #1 (1.50) (1.50) #54 #28 #27 10.16 0.10 ( r 0 . 1 5 ) 22.22 0.10 0.210 0.05 0.665 0.05 ( r 0 . 1 5 ) (0.71) [0.80 0.08] 0.80typ (10 ) 1.00 0.10 0.05 min (10 ) 1.20 max 0.10 max 0.075 max [ [ (10.76) 0.125 +0.075 - 0.035 (10 ) (10 ) 11.76 0.20 (0.80) (0.80) (0.50) (4 ) 0.45 ~ 0.75 (0 8 ) 0.25typ ( r 0 . 2 5 ) ( r 0 . 2 5 ) (0.50) unit : mm note 1. ( ) is reference 2. [ ] is ass?y out quality detail a 0.30 +0.10 - 0.05 detail b 0.35 +0.10 - 0.05 detail b detail a
synchronous dram rev. 1.23 march 2009 6 of 15 k4s280832k K4S281632K bank select data input register 4m x 8 / 2m x 16 4m x 8 / 2m x 16 sense amp output buffer i/o control column decoder latency & burst length programming register address register row buffer refresh counter row decoder col. buffer lras lcbr lcke lras lcbr lwe ldqm clk cke cs ras cas we l(u)dqm lwe ldqm dqi clk add lcas lwcbr 4m x 8 / 2m x 16 4m x 8 / 2m x 16 timing register * samsung electronics reserves the right to ch ange products or specific ation without notice. 5.0 functional block diagram
synchronous dram rev. 1.23 march 2009 7 of 15 k4s280832k K4S281632K pin name input function clk system clock active on the positive going edge to sample all inputs. cs chip select disables or enables device operation by masking or enabling all inputs except clk, cke and dqm cke clock enable masks system clock to freeze oper ation from the next clock cycle. cke should be enabled at least one cycle prior to new command. disable input buffers for power down in standby. a 0 ~ a 11 address row/column addresses are multiplexed on the same pins. row address : ra 0 ~ ra 11 , column address : (x8 : ca 0 ~ ca 9 ), (x16 : ca 0 ~ ca 8 ) ba 0 ~ ba 1 bank select address selects bank to be activated during row address latch time. selects bank for read/write during column address latch time. ras row address strobe latches row addresses on the positive going edge of the clk with ras low. enables row access & precharge. cas column address strobe latches column addresses on the positive going edge of the clk with cas low. enables column access. we write enable enables write operation and row precharge. latches data in starting from cas , we active. dqm data input/output mask makes data output hi-z, t shz after the clock and masks the output. blocks data input when dqm active. dq 0 ~ n data input/output data inputs/outputs are multiplexed on the same pins. (x8 : dq 0 ~ 7 ), (x16 : dq 0 ~ 15 ) v dd /v ss power supply/ground power and ground for the input buffers and the core logic. v ddq /v ssq data output power/ground isolated power supply and ground for the ou tput buffers to provide improved noise immunity. n.c/rfu no connection /reserved for future use this pin is recommended to be left no connection on the device. 54pin tsop (400mil x 875mil) (0.8 mm pin pitch) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v dd dq0 v ddq n.c dq1 v ssq n.c dq2 v ddq n.c dq3 v ssq n.c v dd n.c we cas ras cs ba0 ba1 a10/ap a0 a1 a2 a3 v dd v ss dq7 v ssq n.c dq6 v ddq n.c dq5 v ssq n.c dq4 v ddq n.c v ss n.c/rfu dqm clk cke n.c a11 a9 a8 a7 a6 a5 a4 v ss v dd dq0 v ddq dq1 dq2 v ssq dq3 dq4 v ddq dq5 dq6 v ssq dq7 v dd ldqm we cas ras cs ba0 ba1 a10/ap a0 a1 a2 a3 v dd v ss dq15 v ssq dq14 dq13 v ddq dq12 dq11 v ssq dq10 dq9 v ddq dq8 v ss n.c/rfu udqm clk cke n.c a11 a9 a8 a7 a6 a5 a4 v ss x16 x8 x16 x8 6.0 pin configuration (top view) 7.0 pin function description
synchronous dram rev. 1.23 march 2009 8 of 15 k4s280832k K4S281632K parameter symbol value unit voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on v dd supply relative to v ss v dd , v ddq -1.0 ~ 4.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 1w short circuit current i os 50 ma permanent device damage may occur if "abso lute maximum ratings" are exceeded. functional operation should be restrict ed to recommended operating condition. exposure to higher than recommended voltage for extended per iods of time could affect device reliability. note : recommended operating conditions (voltage referenced to v ss = 0v, t a = 0 to 70 c) parameter symbol min typ max unit note supply voltage v dd , v ddq 3.0 3.3 3.6 v input logic high voltage v ih 2.0 3.0 v dd +0.3 v 1 input logic low voltage v il -0.3 0 0.8 v 2 output logic high voltage v oh 2.4 - - v i oh = -2ma output logic low voltage v ol --0.4vi ol = 2ma input leakage current i li -10 - 10 ua 3 1. v ih (max) = 5.6v ac. the overshoot voltage duration is 3ns. 2. v il (min) = -2.0v ac. the undershoot voltage duration is 3ns. 3. any input 0v v in v ddq . input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. notes : (v dd = 3.3v, t a = 23 c, f = 1mhz, v ref =1.4v 200 mv) pin symbol min max unit clock c clk 2.5 3.5 pf ras , cas , we , cs , cke, dqm c in 2.5 3.8 pf address c add 2.5 3.8 pf (x8 : dq0 ~ dq7), (x16 : dq0 ~ dq15) c out 4.0 6.0 pf 8.0 absolute maximum ratings 9.0 dc operating conditions 10.0 capacitance
synchronous dram rev. 1.23 march 2009 9 of 15 k4s280832k K4S281632K (recommended operating condition unless otherwise noted, t a = 0 to 70 c) parameter symbol test condition version unit note 75 operating current (one bank active) i cc1 burst length = 1 trc trc(min) io = 0 ma 90 ma 1 precharge standby current in power-down mode i cc2 p cke v il (max), tcc = 10ns 2 ma i cc2 ps cke & clk v il (max), tcc = 2 precharge standby current in non power-down mode i cc2 n cke v ih (min), cs v ih (min), tcc = 10ns input signals are changed one time during 20ns 20 ma i cc2 ns cke v ih (min), clk v il (max), tcc = input signals are stable 10 active standby current in power-down mode i cc3 p cke v il (max), tcc = 10ns 5 ma i cc3 ps cke & clk v il (max), tcc = 5 active standby current in non power-down mode (one bank active) i cc3 n cke v ih (min), cs v ih (min), tcc = 10ns input signals are changed one time during 20ns 30 ma i cc3 ns cke v ih (min), clk v il (max), tcc = input signals are stable 25 ma operating current (burst mode) i cc4 io = 0 ma page burst 110 ma 1 refresh current i cc5 trc trc(min) 200 ma 2 self refresh current i cc6 cke 0.2v c2ma3 l800ua4 1. measured with outputs open. 2. refresh period is 64ms. 3. k4s280832k-uc 4. k4s280832k-ul 5. unless otherwise noted, input swing ievei is cmos(v ih /v il =v ddq /v ssq ) notes : 11.0 dc characteristics (x8)
synchronous dram rev. 1.23 march 2009 10 of 15 k4s280832k K4S281632K (recommended operating condition unless otherwise noted, t a = 0 to 70 c) parameter symbol test condition version unit note 50 60 75 operating current (one bank active) i cc1 burst length = 1 trc trc(min) io = 0 ma 140 130 100 ma 1 precharge standby current in power-down mode i cc2 p cke v il (max), tcc = 10ns 2 ma i cc2 ps cke & clk v il (max), tcc = 2 precharge standby current in non power-down mode i cc2 n cke v ih (min), cs v ih (min), tcc = 10ns input signals are changed one time during 20ns 20 ma i cc2 ns cke v ih (min), clk v il (max), tcc = input signals are stable 10 active standby current in power-down mode i cc3 p cke v il (max), tcc = 10ns 5 ma i cc3 ps cke & clk v il (max), tcc = 5 active standby current in non power-down mode (one bank active) i cc3 n cke v ih (min), cs v ih (min), tcc = 10ns input signals are changed one time during 20ns 30 ma i cc3 ns cke v ih (min), clk v il (max), tcc = input signals are stable 25 ma operating current (burst mode) i cc4 io = 0 ma page burst 4banks activated tccd = 2clks 160 150 140 ma 1 refresh current i cc5 trc trc(min) 230 220 200 ma 2 self refresh current i cc6 cke 0.2v c2ma3 l800ua4 1. measured with outputs open. 2. refresh period is 64ms. 3. K4S281632K-uc 4. K4S281632K-ul 5. unless otherwise noted, input swing ievei is cmos(v ih /v il =v ddq /v ssq ) notes : 12.0 dc characteristics (x16)
synchronous dram rev. 1.23 march 2009 11 of 15 k4s280832k K4S281632K (v dd = 3.3v 0.3v, t a = 0 to 70 c) parameter value unit input levels (v ih /v il ) 2.4/0.4 v input timing measurement reference level 1.4 v input rise and fall time tr/tf = 1/1 ns output timing measurement reference level 1.4 v output load condition see fig. 2 3.3v 1200 ? 870 ? output 50pf v oh (dc) = 2.4v, i oh = -2ma v ol (dc) = 0.4v, i ol = 2ma v tt = 1.4v 50 ? output 50pf z0 = 50 ? (fig. 2) ac output load circuit (fig. 1) dc output load circuit notes : (ac operating conditions unless otherwise noted) parameter symbol version unit 50 (x16 only) 60 (x16 only) 75 row active to row active delay trrd(min) 10 12 15 ns ras to cas delay trcd(min) 15 18 20 ns row precharge time trp(min) 15 18 20 ns row active time tras(min) 40 42 45 ns tras(max) 100 us row cycle time trc(min) 55 60 65 ns last data in to row precharge trdl(min) 2 clk last data in to active delay tdal(min) 2 clk + trp - last data in to new col. address delay tcdl(min) 1 clk last data in to burst stop tbdl(min) 1 clk col. address to col. address delay tccd(min) 1 clk number of valid output data cas latency=3 2 ea cas latency=2 - 1 1. the minimum number of clo ck cycles is determined by dividing the minimum time required wi th clock cycle time and then roundi ng off to the next higher integer. 2. minimum delay is required to complete write. 3. all parts allow every cycle column address change. 4. in case of row precharge interrupt, auto precharge and read burst stop. 5. in 100mhz and below 100mhz operating conditions, trdl=1clk and tdal=1clk + 20ns is also supported. samsung recommends trdl=2clk and tdal=2clk + trp. 6. trc =trfc, trdl = twr. 13.0 ac operating test conditions 14.0 operating ac parameter
synchronous dram rev. 1.23 march 2009 12 of 15 k4s280832k K4S281632K parameter symbol condition min typ max unit notes output rise time trh measure in linear region : 1.2v ~ 1.8v 1.37 4.37 volts/ns 3 output fall time tfh measure in linear region : 1.2v ~ 1.8v 1.30 3.8 volts/ns 3 output rise time trh measure in linear region : 1.2v ~ 1.8v 2.8 3.9 5.6 volts/ns 1,2 output fall time tfh measure in linear region : 1.2v ~ 1.8v 2.0 2.9 5.0 volts/ns 1,2 1. rise time specification based on 0pf + 50 ? to v ss , use these values to design to. 2. fall time specification based on 0pf + 50 ? to v dd , use these values to design to. 3. measured into 50pf only, use these values to characterize to. 4. all measurements done with respect to v ss . notes : 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. assumed input rise and fall time (tr & tf) = 1ns. if tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. 4. tss applies for address setup time, clock enable setup time, commend setup time and data setup time tsh applies for address holde time, clock enable hold time, commend hold time and data hold time notes : (ac operating conditions unless otherwise noted) parameter symbol 50 (x16 only) 60 (x16 only) 75 min max min max min max clk cycle time cas latency=3 tcc 5 1000 6 1000 7.5 1000 cas latency=2 - - 10 clk to valid output delay cas latency=3 tsac - 4.5 5 5.4 cas latency=2 - - - 6 output data hold time cas latency=3 toh 2-2.5 3 cas latency=2 - - - 3 clk high pulse width tch 2 - 2.5 2.5 clk low pulse width tcl 2 - 2.5 2.5 input setup time tss 1.5 - 1.5 1.5 input hold time tsh 1 - 1 0.8 clk to output in low-z tslz 1 - 1 1 clk to output in hi-z cas latency=3 tshz - 4.5 5 5.4 cas latency=2 - - - 6 15.0 ac characteristics 16.0 dq buffer output drive characteristics
synchronous dram rev. 1.23 march 2009 13 of 15 k4s280832k K4S281632K i oh characteristics (pull-up) voltage 200mhz 166mhz 133mhz min 200mhz 166mhz 133mhz max (v) i (ma) i (ma) 3.45 -2.4 3.3 -27.3 3.0 0.0 -74.1 2.6 -21.1 -129.2 2.4 -34.1 -153.3 2.0 -58.7 -197.0 1.8 -67.3 -226.2 1.65 -73.0 -248.0 1.5 -77.9 -269.7 1.4 -80.8 -284.3 1.0 -88.6 -344.5 0.0 -93.0 -502.4 i ol characteristics (pull-down) voltage 200mhz 166mhz 133mhz min 200mhz 166mhz 133mhz max (v) i (ma) i (ma) 0.0 0.0 0.0 0.4 27.5 70.2 0.65 41.8 107.5 0.85 51.6 133.8 1.0 58.0 151.2 1.4 70.7 187.7 1.5 72.9 194.4 1.65 75.4 202.5 1.8 77.0 208.6 1.95 77.6 212.0 3.0 80.3 219.6 3.45 81.4 222.6 0 -100 -200 -300 -400 -500 -600 03 0.5 1 1.5 2 2.5 3.5 voltage ma 250 200 150 100 50 0 03 0.5 1 1.5 2 2.5 3.5 voltage ma 200mhz/166mhz /133mhz pull-up 200mhz/166mhz /133mhz pull-down i oh min (200mhz/166mhz/133mhz) i oh max (200mhz/166mhz/133mhz) i oh min (200mhz/166mhz/133mhz) i oh max (200mhz/166mhz/133mhz) 17.0 ibis specification
synchronous dram rev. 1.23 march 2009 14 of 15 k4s280832k K4S281632K v dd clamp @ clk, cke, cs , dqm & dq v dd (v) i (ma) 0.0 0.0 0.2 0.0 0.4 0.0 0.6 0.0 0.7 0.0 0.8 0.0 0.9 0.0 1.0 0.23 1.2 1.34 1.4 3.02 1.6 5.06 1.8 7.35 2.0 9.83 2.2 12.48 2.4 15.30 2.6 18.31 v ss clamp @ clk, cke, cs , dqm & dq v ss (v) i (ma) -2.6 -57.23 -2.4 -45.77 -2.2 -38.26 -2.0 -31.22 -1.8 -24.58 -1.6 -18.37 -1.4 -12.56 -1.2 -7.57 -1.0 -3.37 -0.9 -1.75 -0.8 -0.58 -0.7 -0.05 -0.6 0.0 -0.4 0.0 -0.2 0.0 0.0 0.0 20 15 10 5 0 03 12 voltage ma i (ma) ma i (ma) minimum v dd clamp current (referenced to v dd ) minimum v ss clamp current 0 -10 -20 -30 -40 -3 0 -2 -1 -50 -60 voltage
synchronous dram rev. 1.23 march 2009 15 of 15 k4s280832k K4S281632K (v=valid, x=don t care, h=logic high, l=logic low) command cken-1 cken cs ras cas we dqm ba 0,1 a 10 /ap a 0 ~ a 9, a 11, note register mode register set h x l l l l x op code 1,2 refresh auto refresh h h ll lhx x 3 self refresh entry l 3 exit l h lh hh xx 3 hx x x 3 bank active & row addr. h x l l h h x v row address read & column address auto precharge disable hxlhlhxv l column address 4 auto precharge enable h 4,5 write & column address auto precharge disable h x lhllx v l column address 4 auto precharge enable h 4,5 burst stop h x l h h l x x 6 precharge bank selection hxllhlx vl x all banks xh clock suspend or active power down entry h l hx x x x x lv vv exit l h x x x x x precharge power down mode entry h l hx x x x x lh hh exit l h hx x x x lv vv dqm h x v x 7 no operation command h x hx x x xx lh hh 1. op code : operand code a0 ~ a11 & ba0 ~ ba1 : program keys. (@ mrs) 2. mrs can be issued only at all banks precharge state. a new command can be issued after 2 clk cycles of mrs. 3. auto refresh functions are as same as cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. ba0 ~ ba1 : bank select addresses. if both ba0 and ba1 are "low" at read, write, row active and precharge, bank a is selected. if ba0 is "high" and ba1 is "low" at read, write, row active and precharge, bank b is selected. if ba0 is "low" and ba1 is "high" at read, write, row active and precharge, bank c is selected. if both ba0 and ba1 are "high" at read, write, row active and precharge, bank d is selected. if a10/ap is "high" at row precharge, ba0 and ba1 is ignored and all banks are selected. 5. during burst read or write with auto prec harge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at trp after the end of burst. 6. burst stop command is valid at every burst length. 7. dqm sampled at positive going edge of a clk and masks the data-in at the very clk (write dqm latency is 0), but makes hi-z state the data-out of 2 clk cycles after. (read dqm latency is 2) notes : 18.0 simplified truth table

▲Up To Search▲

Price & Availability of K4S281632K

	To Download K4S281632K Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .